In a circuit, such as a counter, requiring high speed operation, it is a problem how to get fast rise times at various internal circuit nodes. To eliminate the rise time with general enhancement/depletion (E/D) type MOS circuits, a large current depletion-type load device is required to charge the load capacitor fast. However, large current loads require large switch devices, and it causes an increase in the effective load capacitance.
A Dynamic Depletion Mode (DDM) method of getting fast rise times without enlarging the switch size is described in "Dynamic Depletion Mode: An E/D MOS FET Circuit Method for Improved Performance", RONALD W. KNEPPER, IEEE Journal of Solid State Circuits, Vol. SC-13, No. 5, October 1978. But DDM requires many individual circuit elements so that adapting DDM to all large gates produces a very complex logic circuit when a conventional presettable counter is implemented.
A known carry generator consisting of switches in series inherently has the capability of high speed carry transmission because the carry is transmitted by current mode. But this type carry generator cannot be applied to a circuit intended to operate above 1 MHz, because it is difficult to get a high speed rise time at the carry nodes.
Adapting large current load devices to get a fast rise time, the ON resistance of the switch devices is not negligible, and the voltage drop VDS (drain/source) makes the output voltage V.sub.OL level high. Therefore, the operation becomes unstable.
To avoid increasing the V.sub.OL level, the switch size must be enlarged. However if large switch devices are adapted, the large C.sub.Dsub and C.sub.Ssub increases the effective load capacitance of the carry nodes. Consequently the above measures don't achieve the desired objective of fast operation and compact size.
The High Speed Presettable Counter of the present invention overcomes the limitations of the prior art counters and is able to achieve a very high speed of operation, for example 10 MHz.